You will design a Verilog code for a traffic light controller (finite state machine) which will be used at the location: Austin Eluffs Pkwy & Nevada Ave. Problem 1 : Designing a Verilog Code for a Traffic Light Controller Submit your code, a testbench code and test results with waveform. Traffic signal ON duration: Green signal 6 clock cycles, Left signal 3 clock cycles, Yellow signal 1 clock cycle The controller will be started from North/South left signal n/, In states, East/West signal should be red, while North/South Signal should be red in. The controller is based on the finite state machine (FSM) above. Output description Left: 1000 Green: 0100 Yellow: 0010 Red: 0001Įach traffic signal has four lights (left, green, yellow and red) per traffic signal for this design. Each output has 4 bits and each bit will control Left (1000), Green (0100), Yellow (0010) and Red (0001) light as shown in the table. The controller has two input signals (clk, reset), and four output signals - traffic lights (northtl, southtl, easttl and westtl) that are connected to each signal light. You will design a Verilog code for a traffic light controller (finite state machine) which will be used at the location: Austin Eluffs Pkwy Nevada Ave. SOLVED: Problem 1 : Designing a Verilog Code for a Traffic Light Controller
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